There has so far been proposed a parallel processor of the so-called SIMD (Single Instruction Multiple Data) system, in which larger numbers of processors or processing elements (PEs) or arithmetic/logic units are operated in parallel in accordance with a common instruction stream. There has also been proposed a parallel processor of the so-called MIMD (Multiple Instruction Multiple Data) system, in which a plurality of instruction streams are used to operate a plurality of processors or processing units (PUs) or a plurality of arithmetic/logic units with a plurality of instruction streams.
With the parallel processor of the SIMD system, it is sufficient to generate the same single instruction stream for a larger number of PEs, and hence it is sufficient to provide a single instruction cache for generating the instruction stream and a single sequence control circuit for implementing conditional branching. Thus, the parallel processor of the SIMD system has a merit that it has higher performance for a smaller number of control circuits and for a smaller circuit scale, and another merit that, since the operations of the PEs are synchronized with one another at all times, data may be exchanged highly efficiently between the arithmetic/logic units. However, the parallel processor of the SIMD system has a disadvantage that, since there is only one instruction stream, the range of problems that may be tackled with is necessarily restricted.
Conversely, the parallel processor of the MIMD system has a merit that, since a larger number of instruction streams may be maintained simultaneously, an effective range of problems to which the system can be applied is broad. There is however a deficiency proper to the parallel processor of the MIMD system that it is in need of the same number of control circuits as the number of the PEs and hence is increased in circuit scale.
There is also proposed an arrangement of a so-called ‘mixed mode’ parallel processor aimed to achieve the merits of both the SIMD and MIMD systems in such a manner as to enable dynamic switching between SIMD and MIMD systems within the same processor.
For example, there is also disclosed a system in which each processing element (PE) is configured to have a pair of a control circuit and PE so as to enable operation in MIMD mode from the outset and in which all PEs select and execute instruction stream, broadcast over an external instruction bus, in a SIMD mode, while selecting and executing a local instruction stream in a SIMD mode, thereby enabling dynamic switching between a SIMD mode and a MIMD mode (Patent Documents 1 to 4).
[Patent Document 1] JP Patent Kokai Publication No. JP-A59-16071
[Patent Document 2] JP Patent Kokai Publication No. JP-A5-20283
[Patent Document 3] JP Patent No. 2647315
[Patent Document 4] JP Patent No. 3199205